Boolean Algebra Calculator Online – Truth Table, K-Map, SOP/POS, Gate Diagram PNG
What is the Logic Gate & Boolean Algebra Calculator?
This free online tool turns a Boolean expression into a complete digital-logic analysis — truth table, minimized Sum-of-Products (SOP) and Product-of-Sums (POS), Karnaugh map, De Morgan equivalent, and an IEEE-style gate schematic — all computed locally in your browser. Enter (A AND B) OR (NOT C) or symbolic A·B + C' and every result panel updates on each keystroke.
Minimization uses Quine-McCluskey to enumerate prime implicants, then essential prime implicants plus Petrick's method for a minimum cover. Gate diagrams are generated from the parsed expression tree (not a fixed template), so custom inputs produce accurate, input-specific schematics.
Everything runs in WebAssembly (Rust compiled to WASM). Your expressions never leave the browser, and the last expression is saved in localStorage.
Why Use This Tool?
- Homework & exams: Verify truth tables, compare K-map groups with highlighted prime implicants, and copy minimized SOP/POS with one click.
- HDL / FPGA prototyping: Check minterm coverage before writing
assignoralways_combblocks; inspect enable/mask logic from firmware register patterns. - Visual learning: Switch gate diagram modes to see how the same function looks as typed, as minimized SOP, as minimized POS, and after De Morgan's law.
- Export & share: Copy truth table or K-map as CSV; download the current gate diagram as PNG for slides or lab reports.
- Privacy: No server upload — ideal for proprietary chip-enable or security-related logic.
How to Use — Step by Step
- Type or paste a Boolean expression in the Boolean expression textarea, or pick an Examples category and click a tag button to load a sample.
- Use the operator insert buttons (
AND,·,(, etc.) to add tokens at the text cursor. - Variables
A–Z(including multi-letter names likeADDR_MATCH) are auto-detected and ordered alphabetically. The header shows n vars · n minterms and a Clear button. - Review results top to bottom: Truth table → SOP → POS → K-map (2–4 vars) → De Morgan → Gate diagram.
- Copy outputs: Copy CSV on Truth table / K-map; click SOP, POS, or De Morgan result boxes to copy text; Download PNG on the gate diagram for the active mode.
Quick start example:
(A AND B) OR (NOT C)Expected: 8-row truth table (3 vars), minimized SOP AB + C', K-map with grouped minterms, and a gate diagram with AND + NOT + OR in As entered mode.
Input Area
Examples — category dropdown + tag buttons
The Examples dropdown lists categories only (Basics, XOR & comparison, Minimization, De Morgan, Universal gates, Firmware & control). After selecting a category, example expressions appear as tag buttons — click one to replace the textarea with that expression.
Operator insert buttons
Buttons below the textarea insert at the cursor: AND, OR, NOT, XOR, NAND, NOR, XNOR, ·, +, ', ⊕, !, (, ).
Symbol → operator mapping (collapsible)
Expand the mapping table to see word forms, accepted symbols, and operator precedence. The table uses alternating row backgrounds for readability.
Copy & Export
- Truth table — Copy CSV: Header row
A,B,C,Fplus one row per input combination (1/0). - Karnaugh map — Copy CSV: Matrix with row/column Gray-code labels and cell values.
- SOP / POS / De Morgan — click to copy: Click the result box (hint: "Click to copy"). No separate copy button — the entire result area is clickable.
- Gate diagram — Download PNG: Rasterizes the current mode's SVG with theme colors. Filename:
logic-gate-as-entered.png,logic-gate-min-sop.png, etc.
Gate Diagram — Four Modes
Switch modes with the tab buttons in the Gate diagram title row. Each mode uses the same IEEE distinctive-shape renderer (AND semicircle, OR curved body, XOR double curve, inversion bubbles on NAND/NOR/XNOR/NOT).
- As entered: Structural view — one gate per operator you typed. Associative AND/OR/XOR chains merge into one multi-input gate. Each variable drives a vertical track with junction dots where it fans out.
- Minimized SOP: Two-level AND-OR circuit from the Quine-McCluskey minimum cover. Logically equivalent to your input, usually fewer gates than the typed form.
- Minimized POS: Dual of SOP — two-level OR-AND from the minimized maxterm (Product of Sums) cover. Same function, inverted topology (OR gates feed an AND).
- De Morgan: Educational rewrite — a leading NOT on AND/OR/NAND/NOR is pushed through De Morgan's law (e.g.
NOT (A AND B)→(NOT A) OR (NOT B)). Not a minimization pass; XOR/XNOR keep their original shape.
Operator Notation & Precedence
| Operator | Word form | Symbols |
|---|---|---|
| AND | AND | · * & |
| OR | OR | + | |
| NOT | NOT x | !x x' |
| XOR | XOR | ⊕ ^ |
| NAND / NOR / XNOR | NAND NOR XNOR | word form only |
Precedence (highest first): NOT → AND / NAND → XOR / XNOR → OR / NOR. Use parentheses to override — e.g. use (A OR B) AND C instead of ambiguous mixed notation.
Result Panels Explained
- Truth table: Every input combination with output F. Rows where F=1 are highlighted (minterms). Up to 64 rows (6 variables).
- SOP: Minimized Sum of Products — OR of AND terms. Complement shown as
A'. Click the result box to copy. - POS: Minimized Product of Sums — AND of OR terms from maxterms (rows where F=0). Click to copy.
- Karnaugh map: 2–4 variables only. Gray-code axes; colored regions match SOP prime implicants.
- De Morgan: Text equivalent after applying De Morgan's law to complemented AND/OR. Click to copy.
- Gate diagram: Interactive schematic — see Gate Diagram — Four Modes above.
Limitations & Caveats
- 6 variables max: Truth table stops at 64 rows. More variables require external EDA tools.
- K-map: 2–4 variables only. 5–6 variable functions still get truth table + SOP/POS + gate diagrams but no map.
- Single output function: One Boolean expression → one F column. No multi-output or sequential logic.
- NAND/NOR/XNOR symbols: Use word form — there is no single-character symbol for NAND/NOR/XNOR.
- Gate routing is schematic: Orthogonal wires per gate column, not placement-optimized like professional EDA. Dense expressions may have crossing wires.
- Constants 0/1: Fully minimized tautology or contradiction shows a text note instead of gates.
- Bit-mask link: No automatic import from Bit Mask Calculator — copy expressions manually.
Example Categories
Select a category in the Examples dropdown; tag buttons appear below:
- Basics — Simple AND/OR/NOT and symbolic
A·B + C' - XOR & comparison — XOR, XNOR, parity functions
- Minimization — Majority, 4-variable SOP practice
- De Morgan — Complement-of-product and complement-of-sum patterns
- Universal gates — NAND-only and NOR-only constructions
- Firmware & control — Enable/valid/reset, interrupt mask, write strobe (
CS AND (NOT WE) AND ADDR_MATCH)
Typical Scenarios
Digital logic homework
Enter the assigned function, verify the truth table, compare K-map groups with highlighted regions, click SOP to copy the minimized form for submission, and download the gate diagram PNG for your report.
HDL / FPGA combinatorial logic
Prototype assign y = ... conditions by checking minterm coverage. Compare As entered vs Minimized SOP diagrams before refactoring RTL.
Register enable / mask verification
After defining bitfields in Bit Mask Calculator, express CS AND !WE AND ADDR_MATCH here and confirm which address/data combinations assert the output.
De Morgan & POS study
Load a De Morgan category example, read the text equivalent, then switch the gate diagram to De Morgan or Minimized POS to see how complement and dual forms change the circuit topology.
FAQ
Why is there no K-map for my 5-variable function?
K-maps are only rendered for 2, 3, or 4 variables. Use the truth table and minimized SOP/POS for higher variable counts.
Why does SOP differ from what I typed?
SOP is minimized — redundant terms are removed and adjacent minterms are merged. The result is logically equivalent but structurally simpler. Use As entered gate diagram mode to see your original structure.
What is the difference between Minimized SOP and Minimized POS diagrams?
Both implement the same Boolean function. SOP uses a two-level AND-OR network; POS uses OR-AND (OR gates feeding an AND). Gate count is typically similar — choose the form that matches your design style or homework requirement.
What minimization algorithm is used?
Quine-McCluskey to enumerate prime implicants, then essential prime implicants plus Petrick's method (with absorption and a greedy fallback for large covers) for a minimum cover.
Can I use lowercase variable names?
Identifiers are normalized to uppercase. a AND b is treated as A AND B.
How does this relate to the Bit Mask Calculator?
Use Bit Mask Calculator to define register bitfields, then express enable/mask logic as Boolean expressions here for truth-table verification.
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Input
A–Z are auto-detected.| A | B | C | F |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
| A \ BC | 1 | 11 | 1 | |
|---|---|---|---|---|
| — | — | — | — | |
| 1 | — | — | 1 | — |