SPI Calculator – Clock Divider, Transfer Timing, Throughput for AVR, STM32, ESP32
What is SPI?
SPI (Serial Peripheral Interface) is a synchronous full-duplex serial communication protocol developed by Motorola in the 1980s and now ubiquitous in embedded systems. Unlike UART, which is asynchronous and requires both sides to agree on a baud rate, SPI uses a dedicated clock line (SCLK) generated by the master device. This makes SPI significantly faster and simpler to implement in hardware — most modern MCUs include one or more dedicated SPI peripherals.
SPI uses four wires: SCLK (Serial Clock), MOSI (Master Out Slave In), MISO (Master In Slave Out), and CS/SS (Chip Select / Slave Select). The master drives SCLK continuously during a transfer and asserts CS low to address a specific slave. Full-duplex communication happens simultaneously on MOSI and MISO. Multiple slaves can share the SCLK, MOSI, and MISO lines, each addressed by its own dedicated CS line.
SPI is used everywhere in embedded systems: SPI flash memory (W25Q, AT45), SD cards, TFT and e-ink displays (ILI9341, SSD1306), ADC/DAC chips, wireless modules (nRF24L01, CC1101), CAN controllers (MCP2515), sensors (BME280, MPU6050), and more. Its high speed (up to hundreds of MHz on modern silicon) and simplicity make it the first choice for high-bandwidth peripheral communication.
SPI Transfer and Frame Format
An SPI transfer begins when the master asserts CS low. After a CS setup time (t_CSS), the master begins toggling SCLK and simultaneously drives data on MOSI while reading data from MISO. At the end of the transfer, the master deasserts CS high after a CS hold time (t_CSH). There are no start bits, stop bits, or address bytes embedded in the data stream — SPI is purely clock-driven.
- CS Setup (t_CSS) — Minimum time CS must be LOW before the first SCLK edge. Allows the slave to prepare for the incoming transaction. Typically 50–500 ns.
- SCLK cycles — One clock cycle transfers one bit. A word of N bits requires N clock cycles. Most MCU SPI peripherals support 8-bit, 16-bit, and 32-bit word sizes.
- MOSI / MISO — Data shifts out on MOSI and in on MISO simultaneously on each clock edge. Both carry the same number of bits per transfer.
- CS Hold (t_CSH) — Minimum time CS must remain HIGH after the last SCLK edge before the next transaction begins. Typically 50–500 ns.
Example: Transferring 256 bytes at 8 MHz with 8-bit words. Each bit period = 125 ns. Each byte takes 8 × 125 ns = 1 μs. Total data time = 256 μs. With 100 ns setup + 100 ns hold, total transfer time ≈ 256.0002 μs. Throughput ≈ 1.0 MB/s.
CS ______|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|______
SCLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|______
MOSI [CSS] [B7][B6][B5][B4][B3][B2][B1][B0] [CSH]
MISO [---] [D7][D6][D5][D4][D3][D2][D1][D0] [---]How to Use This Calculator
Transfer Timing Calculator
The Transfer Timing tab computes the complete timing profile for an SPI transaction:
- MCU Clock — Select your MCU peripheral clock from 24 presets (1 MHz to 240 MHz) or enter a custom Hz value.
- Clock Divider — The prescaler divides the MCU clock to produce the SPI clock. The effective SPI frequency is shown in the dropdown label. Options: ÷2 through ÷256.
- Transfer Size — Number of bytes to transfer (1–65535). Used to compute total transfer time and throughput.
- Word Size — SPI word width: 8-bit (most common), 16-bit, or 32-bit. Determines how many SCLK cycles per word.
- CS Setup / Hold Time — CS assertion and deassertion margins in nanoseconds. Added to the raw clock time for total transfer duration.
- SPI Mode — One of four modes defined by CPOL and CPHA. Must match the slave device datasheet.
- Bit Order — MSB first (standard) or LSB first. Must match the slave device.
Clock Divider Table
The Clock Divider Table tab shows all 8 SPI prescaler values (÷2 to ÷256) for your selected MCU clock. For each divider you see the resulting SPI clock frequency, bit period, byte period, maximum throughput, and speed classification. The row matching your currently selected divider is highlighted. This helps you quickly identify which divider gives you the speed closest to your target device's maximum SPI clock.
SPI Clock Divider and Prescaler
MCU SPI peripherals generate the SCLK signal by dividing the peripheral bus clock (APB clock on STM32, PCLK on NXP, FCLK on AVR, etc.) by a power-of-2 prescaler. The available dividers vary by MCU family:
- STM32 (F1/F4/H7) — SPI_CR1 BR[2:0] bits select ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, or ÷256 of PCLK.
- AVR (ATmega) — SPCR SPR[1:0] + SPI2X gives ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, or ÷128 of F_CPU.
- ESP32 — SPI clock = APB_CLK (80 MHz) / N, where N is programmable from 1 to 8192.
- RP2040 (Pico) — SPI clock derived from system clock via programmable divider.
- nRF52 — SPI master supports fixed rates: 125 kbps, 250 kbps, 500 kbps, 1 Mbps, 2 Mbps, 4 Mbps, 8 Mbps.
Always check the maximum SPI clock of the slave device and select a divider that produces a frequency at or below that limit. Never exceed the slave's maximum rated SCLK frequency, as this can cause data corruption or device damage.
Common SPI Device Speed Classes
| Device | Max SPI Clock | Notes |
|---|---|---|
| EEPROM (25AA / AT25) | 5–10 MHz | SPI EEPROM, most common sizes 1 Kbit–1 Mbit |
| SD Card (init) | 400 kHz | Mandatory slow clock during card initialization sequence |
| SD Card (data) | 25 MHz | Default speed; SDHC up to 50 MHz in high-speed mode |
| nRF24L01 (2.4 GHz) | 10 MHz | Wireless transceiver; register and payload access |
| BME280 (sensor) | 10 MHz | Temperature, humidity, pressure sensor |
| ILI9341 (TFT display) | 42 MHz | Common 240×320 TFT controller; write faster than read |
| W25Q series (flash) | 80–104 MHz | QSPI/SPI NOR flash; QIO mode up to 133 MHz |
| MCP2515 (CAN controller) | 10 MHz | SPI-to-CAN bridge; register access and message buffers |
| MCP4921 (DAC) | 20 MHz | 12-bit SPI DAC; 16-bit frame |
| ADS1118 (ADC) | 4 MHz | 16-bit delta-sigma ADC with internal reference |
Frequently Asked Questions
What is SPI and how does it work?
SPI is a synchronous full-duplex serial protocol using four wires: SCLK, MOSI, MISO, and CS. The master drives SCLK and CS; data is exchanged simultaneously on MOSI and MISO on each clock edge. There are no start/stop bits — the transfer length is determined by the number of clock cycles issued while CS is asserted low.
What are the four SPI modes (CPOL and CPHA)?
Mode 0 (CPOL=0, CPHA=0): clock idles LOW, data sampled on rising edge. Mode 1 (CPOL=0, CPHA=1): clock idles LOW, sampled on falling edge. Mode 2 (CPOL=1, CPHA=0): clock idles HIGH, sampled on falling edge. Mode 3 (CPOL=1, CPHA=1): clock idles HIGH, sampled on rising edge. Mode 0 is by far the most common. Always match the slave device datasheet.
How is the SPI clock frequency calculated from the MCU clock?
SPI clock = MCU peripheral clock ÷ prescaler. Prescaler values are powers of 2 from 2 to 256. For example, 72 MHz ÷ 4 = 18 MHz SPI clock. Select the largest divisor (slowest SPI clock) that still meets your throughput requirements and stays within the slave device's maximum SCLK frequency.
What is CS setup time and CS hold time in SPI?
CS setup time (t_CSS) is the minimum delay from CS going low to the first SCLK edge. CS hold time (t_CSH) is the minimum time CS stays low after the last SCLK edge before going high. Both are specified in the slave device datasheet. This calculator adds them to the raw clock transfer time to compute the true total transaction time.
What is the maximum SPI clock speed I can use?
The maximum SPI clock is limited by the slave device's rated maximum SCLK frequency. Common limits: 5–10 MHz for SPI EEPROM and CAN controllers, 10 MHz for wireless modules and sensors, 25 MHz for SD cards, 42 MHz for ILI9341 TFT, 80–104 MHz for W25Q flash. PCB trace quality, parasitic capacitance, and pull-up/pull-down values further constrain usable frequency in practice.
What is the difference between SPI and I2C?
SPI is faster (1–50+ MHz vs. I2C's 100 kHz–3.4 MHz), full-duplex, and simpler to implement in hardware — but requires more wires (4 plus one CS per slave vs. I2C's 2 wires with address-based multi-device support). I2C is better for complex multi-device topologies where pin count is constrained. SPI is preferred for high-speed peripherals like flash memory, displays, and data converters.
What does MSB first vs LSB first mean in SPI?
MSB first transmits the most significant bit of each word first — this is the standard for the vast majority of SPI devices. LSB first transmits the least significant bit first, used by some legacy or specialized devices (certain temperature sensors, shift registers). Master and slave must agree on bit order. Most MCU SPI peripherals support both in hardware via a configuration bit.
How do I calculate SPI transfer time and throughput?
Transfer time = (transfer_bytes × word_bits) / SPI_clock_Hz + (CS_setup_ns + CS_hold_ns) / 1,000,000,000. Throughput = transfer_bytes / transfer_time_seconds. For example: 256 bytes, 8-bit words, 8 MHz clock, 100 ns + 100 ns CS overhead: time = (256 × 8) / 8,000,000 + 0.0000002 ≈ 256.0002 μs. Throughput ≈ 1.0 MB/s.
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