I2C Calculator – SCL Timing, TWBR Register, t_HIGH/t_LOW for AVR, STM32, ESP32
What is I2C?
I2C (Inter-Integrated Circuit, sometimes written I²C) is a synchronous half-duplex serial communication protocol developed by Philips Semiconductors (now NXP) in 1982. It uses only two bidirectional wires — SDA (Serial Data) and SCL (Serial Clock) — making it one of the most compact bus protocols in embedded systems. Both lines are open-drain: devices can only pull the lines LOW, and external pull-up resistors return the lines to HIGH when no device is pulling them down. This open-drain topology allows multiple masters and multiple slaves to share the same two-wire bus without dedicated arbiter hardware.
I2C is found on virtually every modern microcontroller and is used to connect sensors, EEPROMs, real-time clocks, DACs, ADCs, display controllers, and more. A single MCU can control dozens of peripherals with just two GPIO pins, with each slave identified by a unique 7-bit (or 10-bit) address. The trade-off is lower throughput and higher protocol overhead compared to SPI — but for configuration registers, sensor readings, and similar low-bandwidth tasks, I2C is the industry standard.
I2C Frame Structure
Every I2C transaction is framed by a START condition and a STOP condition generated by the master. In between, data is transferred in 8-bit bytes, each followed by a 1-bit acknowledgement from the receiver.
- START condition — SDA falls while SCL is HIGH. This signals all slaves to listen for their address.
- Address byte — 7-bit slave address (MSB first) followed by a R/W̅ bit: 0 for write, 1 for read.
- ACK/NACK — After each byte, the receiver pulls SDA LOW (ACK) or leaves it HIGH (NACK) during the 9th clock pulse. A NACK after the address means no slave responded.
- Data bytes — One or more 8-bit data bytes, each followed by an ACK.
- STOP condition — SDA rises while SCL is HIGH. This releases the bus.
- Repeated START — A master can issue a new START without a STOP to change direction (write then read) without releasing the bus.
S | ADDR[6:0] | R/W | ACK | DATA[7:0] | ACK | ... | P
|← 7 bits →| 1 | 1 |← 8 bits →| 1 | |How to Use This Calculator
SCL Timing Calculator
The first tab calculates I2C bus timing parameters for a selected speed mode. Choose Standard (100 kHz), Fast (400 kHz), Fast-plus (1 MHz), High-speed (3.4 MHz), or enter a custom SCL frequency. The result panel shows SCL frequency and period, minimum t_HIGH and t_LOW required by the I2C specification, theoretical bit time, and maximum bus throughput. A frame diagram illustrates the byte structure with a 7-bit address, R/W bit, ACK, and data byte. The timing spec note below the diagram shows the exact limits from the I2C specification for the selected mode.
TWBR Register Calculator
The second tab computes the TWBR (TWI Bit Rate Register) value for AVR microcontrollers (ATmega, ATtiny with hardware TWI). Select your MCU clock, prescaler (TWPS bits in TWSR), and target I2C speed mode. The result card shows the TWBR value to write, the actual SCL frequency achieved, and the error percentage. A comparison table below shows all four I2C speed modes with their TWBR values and errors for the selected MCU clock and prescaler.
I2C Speed Modes and Timing Specification
| Mode | Max SCL | t_HIGH min | t_LOW min | t_r max | t_f max |
|---|---|---|---|---|---|
| Standard (Sm) | 100 kHz | 4.0 µs | 4.7 µs | 1000 ns | 300 ns |
| Fast (Fm) | 400 kHz | 0.6 µs | 1.3 µs | 300 ns | 300 ns |
| Fast-plus (Fm+) | 1 MHz | 260 ns | 500 ns | 120 ns | 120 ns |
| High-speed (Hs) | 3.4 MHz | 60 ns | 160 ns | 40 ns | 40 ns |
Rise time (t_r) is limited by the RC time constant of the pull-up resistor and bus capacitance. For a 400 pF bus with a 4.7 kΩ pull-up: t_r ≈ 0.8473 × R × C ≈ 1590 ns — too slow for Fast mode. Reducing to 1 kΩ: t_r ≈ 338 ns — within Fast-mode spec. Pull-up selection is a key design step when using Fast or Fast-plus modes.
AVR TWBR Register Formula
AVR microcontrollers (ATmega328P, ATmega2560, etc.) implement I2C as TWI (Two-Wire Interface). The SCL frequency is determined by the CPU clock, TWBR value, and the prescaler set by TWPS[1:0] bits in TWSR:
TWBR = (f_cpu / f_scl − 16) / (2 × prescaler)
f_scl = f_cpu / (16 + 2 × TWBR × prescaler)TWBR must be in the range 0–255 (8-bit register). The prescaler multiplies the divisor: TWPS=00 gives ×1, TWPS=01 gives ×4, TWPS=10 gives ×16, TWPS=11 gives ×64. For 16 MHz CPU and 100 kHz I2C with prescaler ×1: TWBR = (16,000,000 / 100,000 − 16) / (2 × 1) = 72. Write TWBR = 72 and clear both TWPS bits in TWSR.
The I2C specification allows a wider error tolerance than UART because the master drives the clock and both sides share the same SCL signal. There is no accumulated error over a frame — the receiver samples SDA on each SCL edge. In practice, errors below ±5% are acceptable for all I2C modes.
Frequently Asked Questions
What is I2C and how does it work?
I2C is a two-wire synchronous serial protocol (SDA + SCL) with open-drain bus topology and pull-up resistors. The master generates the clock and a START condition, then sends a 7-bit slave address with R/W bit. Each byte is acknowledged by the receiver. The master ends with a STOP condition.
What is the difference between I2C Standard, Fast, Fast-plus, and High-speed modes?
Standard: 100 kHz, t_HIGH ≥ 4 µs, t_LOW ≥ 4.7 µs. Fast: 400 kHz, t_HIGH ≥ 0.6 µs. Fast-plus: 1 MHz, t_HIGH ≥ 260 ns, requires stronger drive current. High-speed: 3.4 MHz, requires a master code handshake and current-source pull-ups. Most devices support Standard and Fast.
How is the TWBR register calculated for AVR microcontrollers?
TWBR = (f_cpu / f_scl − 16) / (2 × prescaler). The prescaler is set by TWPS bits in TWSR: 1, 4, 16, or 64. For 16 MHz / 100 kHz / prescaler 1: TWBR = (160 − 16) / 2 = 72.
What are pull-up resistors and why does I2C need them?
I2C uses open-drain outputs — devices can only pull lines LOW. External pull-up resistors pull lines HIGH when released. The resistor value is a speed vs. power trade-off: 4.7 kΩ for Standard, 1–2.2 kΩ for Fast. Too high a value and the rise time (t_r) exceeds the spec limit for the mode.
What is the difference between 7-bit and 10-bit I2C addressing?
7-bit addressing gives 128 addresses (16 reserved). 10-bit extends to 1024 addresses using a two-byte prefix sequence (11110xx + 8-bit LSBs). Most devices use 7-bit addressing. Both modes can coexist on the same bus.
What is clock stretching in I2C?
A slave can hold SCL LOW to pause the transaction when it needs more time to process data. Since both SDA and SCL are open-drain, the slave just holds SCL LOW after the master releases it. Not all slaves implement clock stretching, and some masters (especially bit-banged ones) do not handle it.
What is an ACK and NACK in I2C?
After each 8-bit byte, the receiver drives SDA LOW during the 9th clock pulse (ACK = accepted) or leaves it HIGH (NACK = rejected or end of read). A NACK after the address byte means no device at that address responded.
Can I2C be used for long-distance communication?
I2C is designed for on-board use — bus capacitance is limited to 400 pF (Standard/Fast), restricting cable length to roughly 1–2 m. For longer distances use RS-485, CAN, or LIN. Bus extenders like PCA9600 can increase range by resetting the capacitance.
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