Bit Mask Calculator – Visual Bit Builder, Register SET/CLEAR/TOGGLE/READ, C Macro Generator

Build bitmasks visually on an 8/16/32/64-bit grid, generate C #define macros, and apply SET, CLEAR, TOGGLE, or READ operations to register values with bit layout visualization and C code output.

What is a Bit Mask Calculator?

A bit mask calculator helps embedded engineers and firmware developers build, visualize, and apply bitmasks to hardware registers. In embedded systems, nearly every peripheral — GPIO, UART, SPI, I2C, timer — is configured by writing specific bits in memory-mapped registers. Directly writing a full byte risks overwriting configuration bits you need to preserve. Bit mask operations let you modify only the bits you intend to change while leaving all other bits untouched.

This tool provides two workflows in one place: the Bit Mask Builder lets you click individual bits on a visual grid to construct a mask, then instantly see the value in HEX, DEC, and BIN along with a ready-to-paste C #define macro. The Register Bit Field tab takes any register value and mask, applies SET, CLEAR, TOGGLE, or READ operations, and shows the before/after bit layout with generated C code.

All computation runs entirely in your browser via WebAssembly. No register values or mask data leave your machine. Supports 8, 16, 32, and 64-bit widths, compatible with AVR, STM32, ESP32, ARM Cortex-M, RISC-V, and any other architecture.

How to Use the Bit Mask Builder

  1. Select Bit Width — Choose 8, 16, 32, or 64 bits to match your register size.
  2. Click Bits to Toggle — Each cell represents one bit. Bit 0 (LSB) is at the right; the MSB is at the left. Blue = 1, grey = 0. Click any bit to toggle it.
  3. Name Your Mask — Enter a macro name (e.g. LED_PIN or USART_RX_EN). The tool generates the C #define automatically.
  4. Copy Results — Click any output value or code snippet to copy it to the clipboard.
  5. Apply to Register — Switch to the Register Bit Field tab to apply your mask to a register value.

Bit Mask Operations Reference

SET — Turn Bits On

reg |= mask; /* set all 1-bits in mask */

Example: reg=0x50 (0101 0000), mask=0x07 (0000 0111) → result=0x57 (0101 0111)

Use case: Enable a peripheral, set GPIO output high, configure mode bits.

CLEAR — Turn Bits Off

reg &= ~mask; /* clear all 1-bits in mask */

Example: reg=0xFF (1111 1111), mask=0x0F (0000 1111) → result=0xF0 (1111 0000)

Use case: Disable a feature, set GPIO output low, reset a status flag.

TOGGLE — Flip Bits

reg ^= mask; /* flip all 1-bits in mask */

Example: reg=0xAA (1010 1010), mask=0xFF (1111 1111) → result=0x55 (0101 0101)

Use case: Blink an LED, create PWM-like output, detect bit changes.

READ — Extract a Bit Field

field = (reg & mask) >> shift; /* isolate and right-shift */

Example: reg=0xB4 (1011 0100), mask=0x38 (0011 1000), shift=3 → field=0x06 (110)

Use case: Read ADC channel selection bits, read prescaler value, decode UART config.

Practical Examples — MCU Register Configuration

STM32 GPIO Mode Register (MODER)

The STM32 GPIOA_MODER is a 32-bit register where each GPIO pin occupies 2 bits: 00=Input, 01=Output, 10=Alternate Function, 11=Analog.

To configure PA5 as Output, clear and then set bits [11:10]:

/* Clear bits [11:10] */

GPIOA->MODER &= ~(0x3u << 10); /* mask = 0x00000C00 */

/* Set Output mode (01) */

GPIOA->MODER |= (0x1u << 10); /* mask = 0x00000400 */

AVR UART Control Register (UCSR0B)

The ATmega UCSR0B register controls UART enable bits: bit4=RXEN0 (RX Enable), bit3=TXEN0 (TX Enable).

#define RXEN0_MASK (1u << 4) /* 0x10 */

#define TXEN0_MASK (1u << 3) /* 0x08 */

UCSR0B |= RXEN0_MASK | TXEN0_MASK; /* enable TX and RX */

ESP32 GPIO Output Enable Register

ESP32 uses a SET/CLEAR register pair to avoid read-modify-write cycles:

GPIO.enable_w1ts.val = (1u << pin_num); /* set output enable */

GPIO.enable_w1tc.val = (1u << pin_num); /* clear output enable */

This hardware pattern eliminates race conditions in interrupt-heavy code.

Frequently Asked Questions — Bit Mask Calculator

What is a bit mask?

A bit mask is an integer value used to select specific bits in a larger value. Bits set to 1 in the mask indicate the target bits. Used with | to set bits, &~ to clear bits, ^ to toggle bits, and & to extract a bit field. In embedded programming, masks are usually defined as C macros: #define CTRL_EN (1u << 3).

How do I set a bit without changing other bits?

Use reg |= (1u << n) to set bit n while preserving all other bits. The OR operation only changes bits where the mask has a 1. For hardware registers, use a volatile pointer: *((volatile uint32_t*)ADDR) |= MASK;.

How do I clear a bit?

Use reg &= ~(1u << n). The NOT (~) flips all bits in the mask (so bit n becomes 0, all others become 1), and AND preserves bits where the inverted mask is 1. Never use reg = reg & ~mask if reg is a read-only or write-only hardware register — check your MCU datasheet.

What is the difference between a bit mask and a bit field?

A bit mask is the bitmask value itself (e.g. 0x0C = bits [3:2]). A bit field is the multi-bit value stored at those bit positions within a register. To extract a bit field: mask first with AND, then shift right by the lowest bit position. This tool's READ operation automates both steps and shows the extracted field value.

Why use 'u' suffix on mask literals in C?

Without the 'u' suffix, integer literals are signed. Bitwise NOT of a signed value can sign-extend to unexpected widths, and right-shift of negative signed values is implementation-defined. The 'u' suffix forces unsigned type, giving fully defined behavior for all bit operations. For 32-bit masks, use 0x...u or (uint32_t)0x... to be explicit.

How do I modify bits in a hardware register safely?

Always use read-modify-write with volatile: volatile uint32_t *reg = (volatile uint32_t*)ADDR; *reg |= MASK; For registers where R-M-W creates race conditions (shared between ISR and main), use atomic operations or a SET/CLEAR register pair if your MCU provides them (like ESP32 GPIO_W1TS / GPIO_W1TC or STM32 BSRR).

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Mask Settings

8 Bit Grid
click bit to toggle
70
60
50
40
30
20
10
00
1 — selected0 — cleared
Output Values click to copy
HEX
0x00
DEC
0
BIN
0b00000000
Set Bits
— none —
C Macro
#define MY_MASK click to copy
#define MY_MASK ((8-bit)0x00u)
Bit numbering starts at 0 (LSB). The MSB is at the left of the grid. For 32-bit registers, bit 31 is the most significant bit.
Working with serial protocol timing? Use the UART Calculator, SPI Calculator, or I2C Calculator to cross-reference register configuration with timing.